说明
The XIO2200A is a single-function PCI Express to PCI translation bridge where the PCI bus interface is internally connected to a 1394a open host controller link-layer controller with a two-port 1394a PHY. The PCI-Express to PCI translation bridge is fully compatible with the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. Also, the bridge supports the standard PCI-to-PCI bridge programming model. The 1394a OHCI controller function is fully compatible with IEEE Standard 1394a-2000 and the latest 1394 Open Host Controller Interface (OHCI) Specification.
For downstream traffic, the PCI Express to PCI translation bridge simultaneously supports up to eight posted and four nonposted transactions for each enabled virtual channel (VC).
特性
- Full x1 PCI Express Throughput
- Fully Compliant with PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
- Fully Compliant with PCI Express Base Specification, Revision 1.0a
- Fully Compliant with PCI Local Bus Specification, Revision 2.3
- A Second Virtual Channel for Quality-of-Service and Isochronous Applications
- Advanced PCI Isochronous Windows for Memory Space Mapping to a Specified Traffic Class
- Utilizes 100-MHz Differential PCI Express Common Reference Clock or 125-MHz Single-Ended Reference Clock
- Fully Compliant With Provisions of IEEE Std 1394-1995 for a High-Performance Serial Bus and IEEE Std 1394a-2000.
- Fully Compliant with 1394 Open Host Controller Interface Specification, Revision 1.1
- Full IEEE Std 1394a-2000 Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation Arbitration Acceleration, Fly-by Concatenation, and Port Disable/Suspend/Resume
- Two IEEE Std 1394a-2000 Fully Compliant Cable Ports at 100M Bits/s, 200M Bits/s, and 400M Bits/s
- Cable Ports Monitor Line Conditions for Active Connection To Remote Node
- Cable Power Presence Monitoring
- EEPROM Configuration Support to Load the Global Unique ID for the 1394 Fabric
- Wake Event and Beacon Support
- Support for D1, D2, D3hot, and D3cold
- Active State Link Power Management Saves Power When Packet Activity on the PCI Express Link is Idle, Using Both L0s and L1 States
- Integrated AUX Power Switch Drains VAUX Power Only When Main Power Is Off
- Eight 3.3-V, Multifunction, General-Purpose I/O Terminals
- Compact Footprint, 176-Ball, GGW MicroStar™ BGA, Lead-Free 176-Ball, ZGW MicroStar™ BGA, or Lead-Free 175-ball, ZHH MicroStar™ BGA
