• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The TSB82AA2B OHCI-Lynx. controller is a discrete 1394b link-layer device, which has been designed to meet the demanding requirements of today's 1394 bus designs. The TSB82AA2B device is capable of exceptional 800M bits/s performance; thus, providing the throughput and bandwidth to move data efficiently and quickly between the PCI and 1394 buses. The TSB82AA2B device also provides outstanding ultra-low power operation and intelligent power management capabilities. The device provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, 400M bits/s, and 800M bits/s serial bus data rates.

The TSB82AA2B improved throughput and increased bandwidth make it ideal for today's high-end PCs and open the door for the development of S800 RAID- and SAN-based peripherals.

特性

• Single 3.3-V supply (1.8-V internal core voltage with regulator)
• 3.3-V and 5-V PCI signaling environments
• Serial bus data rates of 100M bits/s, 200M bits/s, 400M bits/s, and 800M bits/s
• Physical write posting of up to three outstanding transactions
• Serial ROM or boot ROM interface supports 2-wire serial EEPROM devices
• 33-MHz/64-bit and 33-MHz/32-bit selectable PCI interface
• Multifunction terminal (MFUNC terminal 1)
  • PCI_CLKRUN protocol per the PCI Mobile Design Guide
  • General-purpose I/O
  • CYCLEIN/CYCLEOUT for external cycle timer control for customized synchronization
• PCI burst transfers and deep FIFOs to tolerate large host latency
  • Transmit FIFO—5K asynchronous
  • Transmit FIFO—2K isochronous
  • Receive FIFO—2K asynchronous
  • Receive FIFO—2K isochronous
• D0, D1, D2, and D3 power states and PME events per the PCI Bus Power Management Interface Specification
• Programmable asynchronous transmit threshold
• Isochronous receive dual-buffer mode
• Out-of-order pipelining for asynchronous transmit requests
• Register access fail interrupt when the PHY SYSCLK is not active