• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The TSB43Ex42/43 is high-performance consumer electronics IEEE 1394 link layer and integrated physical layer devices designed for digitally interfacing advanced video consumer electronics applications. It supports formatting and transmission of IEC61883 data, including IEC61883-1 (general), IEC61883-2 (SD-DVCR), IEC61883-4 (MPEG2-TS), and IEC61883-7 (ITU-R BO.1294 SystemB-DSS). The TSB43Ex42/43 also supports standard IEEE 1394 data types, such as asynchronous, asynchronous streams, and PHY packets.

The TSB43EAxx/ECxx version incorporates DTCP (M6) baseline per the DTLA (5C) specification to support transmit and receive of up to two MPEG2 transport streams with encryption and decryption. The TSB43EAxx/ECxx version also includes hardware acceleration for content key generation.

特性

• IEEE 1394 Features
  • Integrated 400/200/100-Mbps 2-Port/3-Port PHY
  • Compliant to IEEE Std 1394-1995 and IEEE Std 1394a-2000
  • Supports Bus Manager Functions and Automatic 1394 Self-ID Verification
  • Separate Asynchronous ACK Buffers Decrease ACK-Tracking Burden on External CPU
• DTCP and AES Encryption Support for MPEG-DVB and DSS
  (TSB43EA42/43 and TSB43EC42/43 Only)
  • DTCP Encryption Support on IEEE Std 1394 Bus
  • AES128 Encryption Support on HSDI Path (TSB43EC42/43 Only)
  • Support for up to Two Encrypted/Decrypted Streams at One Time
  • Full or Restricted AKE Performed With Hardware Assist
  • Secure Loading of DTCP and AES128 Information Using External CPU Interface
  • Localization Support Compliant With DTCP Draft Revision 1.51
• Video Interfaces
  • Two Configurable High-Speed Data Ports for Video Data
    • One Port Configurable As Parallel Or Serial
    • One Port Serial Only
  • Pass-Through Modes for HSDI0 and HSDI1
  • Packet Insertion – Two Insertion Buffers per HSDI for PAT, PMT, SIT, and DIT Packets
  • PID Filtering (32 PID Filters per HSDI Port)
• External CPU Interfaces