说明
The Texas Instruments TSB43AB23 device is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification (Revision 1.1), IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification (Release 1.1). It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The TSB43AB23 device provides three 1394 ports that have separate cable bias (TPBIAS). The TSB43AB23 device also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements.
As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable.
特性
- Fully compliant with 1394 Open Host Controller Interface Specification (Release 1.1)
- Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus
and IEEE Std 1394a-2000
- Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394
- Compliant with Intel Mobile Power Guideline 2000
- Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume
- Power-down features to conserve energy in battery-powered applications include: automatic device power down during suspend, PCI power management for link-layer, and inactive ports powered down
- Ultralow-power sleep mode
- Three IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s
- Cable ports monitor line conditions for active connection to remote node
- Cable power presence monitoring
- Separate cable bias (TPBIAS) for each port
- 1.8-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
- Physical write posting of up to three outstanding transactions
- PCI burst transfers and deep FIFOs to tolerate large host latency
- PCI_CLKRUN\ protocol
- External cycle timer control for customized synchronization
- Extended resume signaling for compatibility with legacy DV components
- PHY-link logic performs system initialization and arbitration functions
- PHY-link encode and decode functions included for data-strobe bit level encoding
- PHY-link incoming data resynchronized to local clock
