说明
The TSB41LV04A provides the digital and analog transceiver functions needed to implement a four-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41LV04A is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A.
The TSB41LV04A requires only an external 24.576 MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.
特性
- Fully Supports Provisions of IEEE 1394-1995 Standard for High-Performance Serial Bus
and the P1394a Supplement
- Fully Interoperable with FireWireTM and i.LINKTM Implementation of IEEE Std 1394
- Fully Compliant With OpenHCI Requirements
- Provides Four P1394a Fully-Compliant Cable Ports at 100/200/400 Megabits per Second (Mbits/s)
- Full P1394a Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-By Concatenation, Port Disable/Suspend/Resume
- Extended Resume Signaling for Compatibility With Legacy DV Devices
- Power-Down Features to Conserve Energy in Battery-Powered Applications Include: Automatic Device Power-Down during Suspend, Device Power-Down Terminal, Link Interface Disable Via LPS, and Inactive Ports Powered-Down
- Ultralow-Power Sleep Mode
- Node Power Class Information Signaling for System Power Management
- Cable Power Presence Monitoring
- Cable Ports Monitor Line Conditions for Active Connection to Remote Node
- Register Bits Give Software Control of Contender Bit, Power Class Bits, Link Active Control Bit and P1394a Features
- Data Interface to Link-Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz
- Interface to Link-Layer Controller Supports Low-Cost TI Bus-Holder Isolation and Optional Annex J Electrical Isolation
- Interoperable With Link-Layer Controllers Using 3.3-V and 5-V Supplies
- Interoperable With Other Physical Layers (PHYs) Using 3.3-V and 5-V Supplies
- Low-Cost 24.576-MHz Crystal Provides Transmit, Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz
- Incoming Data Resynchronized to Local Clock
- Logic Performs System Initialization and Arbitration Functions
- Encode and Decode Functions Included for Data-Strobe Bit Level Encoding
