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产品名称：TSB41AB1
产品封装：48HTQFP, 64BGA MICROSTAR JUNIOR, 64HTQFP, 80BGA
产品品牌：Texas Instruments
PDF文档：下载
库 存：查看
电 话：0755-83035811
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产品介绍
说明
The TSB41AB1 provides the digital and analog transceiver functions needed to implement a one-port node in a cable-based IEEE 1394 network. The cable port incorporates one differential line transceiver. The transceiver includes circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41AB1 is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A.
The TSB41AB1 requires only an external 24.576-MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.
特性
- Fully Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus† and IEEE 1394a-2000
- Fully Interoperable With FireWire™ and i.LINK™ Implementation of IEEE Std 1394
- Fully Compliant With OpenHCI Requirements
- Provides One IEEE 1394a-2000 Fully Compliant Cable Port at 100/200/400 Megabits Per Second (Mbits/s)
- Full IEEE 1394a-2000 Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-By Concatenation, Port Disable/Suspend/Resume
- Register Bits Give Software Control of Contender Bit, Power Class Bits, Link Active Control Bit, and IEEE 1394a-2000 Features
- IEEE 1394a-2000 Compliant Common Mode Noise Filter on Incoming TPBIAS
- Extended Resume Signaling for Compatibility With Legacy DV Devices, and Terminal- and Register-Compatibility With TSB41LV01, Allow Direct Isochronous Transmit to Legacy DV Devices With Any Link Layer Even When Root
- Power-Down Features to Conserve Energy in Battery Powered Applications Include: Automatic Device Power Down During Suspend, Device Power-Down Terminal, Link Interface Disable via LPS, and Inactive Ports Powered Down
- Failsafe Circuitry Senses Sudden Loss of Power to the Device and Disables the Port to Ensure That the Device Does Not Load TPBIAS of the Connected Device and Blocks Any Leakage Path From the Port Back to the Device Power Plane
- Software Device Reset (SWR)
- Industry Leading Low Power Consumption
- Ultralow-Power Sleep Mode
- Cable Power Presence Monitoring
- Cable Ports Monitor Line Conditions for Active Connection to Remote Node
- Data Interface to Link-Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz
- Interface to Link Layer Controller Supports Low Cost TI Bus-Holder Isolation and Optional Annex J Electrical Isolation
- Interoperable With Link-Layer Controllers Using 3.3 V
- Single 3.3-V Supply Operation
- Low-Cost 24.576-MHz Crystal Provides Transmit, Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz
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