• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The TPD2S017 provides a robust system-level ESD solution for the high-speed lines interfacing low-voltage, ESD-sensitive core chipset. This device offers two stage ESD clamps in each line with 1- series resistor isolation. This architecture allows the device to generate very low clamp voltage during system level ESD strikes. Due to the series resistor component, the TPD2S017 provides a controlled filter roll-off for even greater spurious EMI suppression and signal integrity. This device offers a flow-through pin mapping for ease of board layout. The monolithic silicon technology allows matching component values, including clamp capacitance, series resistor matching, etc., between the differential signal pairs. Tight matching of the line capacitance and series resistors ensure that the differential signal distortion due to added ESD clamp remains minimal, and also allow the part to operate at high-speed differential data rate (in excess of 1.

特性

• Ultra-Low Clamp Voltage Ensures the Protection of
  Ultra-Low Voltage Core Chipset During ESD Events
• Exceeds ESD Protection to IEC61000-4-2 (Level 4)
• Matching of Series Resistor (R =1 ) of ±8 m (Typical)
• Differential Channel Input Capacitance Matching of 0.02 pF (Typical)
• High-Speed Data Rate and EMI Filter Action at High Frequencies
  (–3 dB Bandwidth, 3 GHz)
• Available in 6-Pin Small-Outline Transistor [SOT (DBV)] Package
• Flow-Through Single-In-Line Pin Mapping for the High-Speed
  Lines Ensures no Additional Board Layout Burden While Placing
  the ESD Protection Chip Near the Connector
• APPLICATIONS
  • Hi-Speed USB
  • IEEE 1394 Interface
  • Low-Voltage Differential Signaling (LVDS)
  • Mobile Display Digital Interface (MDDI)/Mobile
    Industry Processor Interface (MIPI)
  • HS Signal