• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The TMS320VC5502 (5502) fixed-point digital signal processor (DSP) is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity.

The C55x™ CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle.

特性

• High-Performance, Low-Power, Fixed-Point TMS320C55x™ Digital Signal Processor (DSP)
  • 3.33-/5-ns Instruction Cycle Time
  • 300-/200-MHz Clock Rate
  • 16K-Byte Instruction Cache (I-Cache)
  • One/Two Instructions Executed per Cycle
  • Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)]
  • Two Arithmetic/Logic Units (ALUs)
  • One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses
• Instruction Cache (16K Bytes)
• 32K x 16-Bit On-Chip RAM That is Composed of Eight Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (64K Bytes)
• 16K × 16-Bit One-Wait-State On-Chip ROM (32K Bytes)
• 8M × 16-Bit Maximum Addressable External Memory Space
• 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to:
  • Asynchronous Static RAM (SRAM)
  • Asynchronous EPROM
  • Synchronous DRAM (SDRAM)
  • Synchronous Burst RAM (SBRAM)
• Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values
• Programmable Low-Power Control of Six Device Functional Domains
• On-Chip Peripherals