• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The TMS320DM6467T (also referenced as DM6467T) leverages TI's DaVinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6467T enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6467T provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data.

特性

• High-Performance Digital Media SoC
  • 1-GHz C64x+™ Clock Rate
  • 500-MHz ARM926EJ-S™ Clock Rate
  • Eight 32-Bit C64x+ Instructions/Cycle
  • 8000 C64x+ MIPS
  • Fully Software-Compatible With C64x / ARM9™
  • Industrial Temperature Devices Available
• Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
  • Eight Highly Independent Functional Units
    • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
    • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
  • Load-Store Architecture With Non-Aligned Support
  • 64 32-Bit General-Purpose Registers
  • Instruction Packing Reduces Code Size
  • All Instructions Conditional
  • Additional C64x+™ Enhancements
    • Protected Mode Operation Exceptions
    • Support for Error Detection and Program Redirection
    • Hardware Support for Modulo Loop Operation
• C64x+ Instruction Set Features