TMS320C6424-500 定点数字信号处理器

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首页 >> 产品展示 >> 集成电路 >> 数字信号处理(DSP)系统 >> TMS320C6424-500

产品名称：TMS320C6424-500

产品封装：361NFBGA, 376BGA

产品品牌：Texas Instruments

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产品介绍

说明

The TMS320C64x+™ DSPs (including the TMS320C6424 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6424 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital signal processor applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

特性

High-Performance Digital Signal Processor (C6424)
- 2.5-, 2-, 1.67, 1.43-ns Instruction Cycle Time
- 400-, 500-, 600-MHz C64x+™ Clock Rate
- Eight 32-Bit C64x+ Instructions/Cycle
- 3200, 4000, 4800, 5600 MIPS
- Fully Software-Compatible With C64x
- Commercial and Automotive (Q or S suffix)Grades
- Low-Power Device (L suffix)
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2 Extensions:
  - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Additional C64x+™ Enhancements
  - Protected Mode Operation
  - Exceptions Support for Error Detection and Program Redirection
  - Hardware Support for Modulo Loop Auto-Focus Module Operation