• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The TMS320C5504 is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The TMS320C5504 fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle.

器件用途

• Wireless Audio Devices (e.g., Headsets, Microphones, Speakerphones, etc.)
• Echo Cancellation Headphones
• Portable Medical Devices
• Voice Applications
• Industrial Controls
• Fingerprint Biometrics
• Software Defined Radio
• Community Resources
  • TI E2E Community
  • TI Embedded Processors Wiki

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All other trademarks are the property of their respective owners.

特性

• High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
  • 16.67-, 13.33, 10-, 8.33-, 6.66ns Instruction Cycle Time
  • 60-, 75-, 100-, 120-MHz Clock Rate
  • One/Two Instruction(s) Executed per Cycle
  • Dual Multipliers [Up to 200, 240 or 300 Million Multiply-Accumulates per Second (MMACS)]
  • Two Arithmetic/Logic Units (ALUs)
  • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
  • Fully Software-Compatible With C55x Devices
  • Industrial Temperature Devices Available
• 256 K Bytes Zero-Wait State On-Chip RAM, Composed of:
  • 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K × 16-Bit
  • 192K Bytes of Single-Access RAM (SARAM), 24 Block of 4K × 16-bit
• 128K Bytes of Zero Wait-State On-Chip ROM (4 Blocks of 16K × 16-Bit)
• 4M × 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)
• 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
  • 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
  • 8-/16-Bit NOR Flash
  • Asynchronous Static RAM (SRAM)
  • 16-bit SDRAM/mSDRAM (1.8-, 2.5-, and 3.3-V)
• Direct Memory Access (DMA) Controller