• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The TLK3118 is a flexible, redundant XAUI serial transceiver that is compliant to 10-Gbps Ethernet XAUI specification. The TLK3118 provides high-speed bi-directional point-to-point data transmissions with up to 12.5 Gbps of raw data transmission capacity. The primary application of this device for use in backplanes and front panel connections requiring redundant 10Gbps connections over controlled impedance media of approximately 50 . The transmission media can be printed circuit board (PCB) traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling into the lines.

The TLK3118 performs the parallel-to-serial, serial-to-parallel conversion, and clock extraction functions for a physical layer interface.

特性

• Redundant Quad 3.2-Gbps Transceiver Configurable as 10-Gbps Attachment Unit Interface (XAUI) Transceiver
• IEEE P802.3ae-2002 10 Gbps Ethernet XGXS (XGMII Extender Sublayer) Compliant
• Redundancy: Fast Switching from Primary to Secondary XAUI channel with Provisionable Error Character or Local Code Fault Insertion at Switch Time
• XAUI: Transmit Pre-Emphasis and Receive Adaptive Equalization to Allow Extended Backplane Reach
• Selectable Full Duplex XAUI Retimer Mode
• Support PRBS 2⁷-1 and 2²³ -1 Generate/verify. Support Standard Defined CJPAT, CRPAT, High Freq, Low Freq, and Mixed Freq testing
• XGMII: HSTL Class 1 I/O with On-Chip 50- Termination on Inputs/Outputs
• XGMII: Source Centered Timing
• Supports Jumbo Packet (9600 byte maximum) Operation
• Align Character Skew Support of 40 bit times at Chip Pins
• MDIO: IEEE 802.3ae Clause 45 Compliant Management Data Input/Output Interface
• 1.2-V Core Voltage Supply, 1.5-V HSTL I/O Supply, and 2.5-V LVCMOS and Bias Supply
• JTAG: IEEE 1149.1 Test Interface
• Fabricated in Advanced 130-nm CMOS Technology
• Package: Small Footprint 21x21mm, 400-Ball, Fine Pitch (1mm) PBGA