• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The TL16PIR552 has a dual-channel universal asynchronous receiver/transmitter (UART). The UART is similar to the TL16C550C. The device serves two serial input/output ports simultaneously in microcomputer or microprocessor-based systems. Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the dual UART can be read by the CPU at any time during functional operation. The information obtained includes the type and condition of the transfer operation being performed and the error condition.

The receiver and transmitter FIFOs in the UARTs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO.

特性

• Dual TL16C550C Universal Asynchronous Receiver/Transmitters (UARTs)
• IEEE 1284 Bidirectional Parallel Data (PD) Port
  • Compatible With Standard Centronics Parallel Interface
  • Support for Parallel Protocols: Extended Capability Port (ECP) and Enhanced Parallel Port (EPP)
  • Data Path 16-Byte FIFO Buffer
  • Direct Memory Access (DMA) Transfer
  • Decompression of Run Length Encoded Data in ECP Reverse Mode
  • Direct Connection to Printer, No External Transceiver is Needed
• Serial Ports Have Infrared Data Association (IrDA) Inputs and Outputs
  • 1200 bps to 115.2 kbps Data Rate
• 16-Byte FIFOs Reduce CPU Interrupts
• 12 mA Drive Current for All 1284 Control Terminals and Parallel Port Data Terminals
• Programmable Auto Flow Control on the UARTs
• Capable of Running With All Existing TL16C450 Software
• After Reset, All Registers Are Identical to the TL16C450 Register Set
• Up to 16-MHz Clock Rate for Up to 1-Mbaud Operation
• In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
• Programmable Baud-Rate Generator Allows Division of Any Input Reference Clock by 1 to (2¹⁶ -1) and Generates an Internal 16× Clock
• Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or From the Serial Data Stream
• On-Board Prescaler With Programmable Divisor Values From 0 to 33