• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The TL16C752B is a dual universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 3 Mbps. The TL16C752B offers enhanced features. It has a transmission control register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.

The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on the RX signal.

特性

• Pin Compatible With ST16C2550 With Additional Enhancements
• Up to 1.5 Mbps Baud Rate When Using Crystal (24-MHz Input Clock)
• Up to 3 Mbps Baud Rate When Using Oscillator or Clock Source
  (48-MHz Input Clock)
• 64-Byte Transmit FIFO
• 64-Byte Receive FIFO With Error Flags
• Programmable and Selectable Transmit and Receive FIFO Trigger
  Levels for DMA and Interrupt Generation
• Programmable Receive FIFO Trigger Levels for Software/Hardware
  Flow Control
• Software/Hardware Flow Control
  • Programmable Xon/Xoff Characters
  • Programmable Auto-RTS and Auto-CTS
• Optional Data Flow Resume by Xon Any Character
• DMA Signalling Capability for Both Received and Transmitted Data
• Supports 3.3-V Operation
• Software Selectable Baud Rate Generator
• Prescaler Provides Additional Divide By 4 Function
• Fast Access Time 2 Clock Cycle IOR/IOW Pulse Width
• Programmable Sleep Mode
• Programmable Serial Interface Characteristics
  • 5-, 6-, 7-, or 8-Bit Characters
  • Even, Odd, or No Parity Bit Generation and Detection