• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The TL16C750 is a functional upgrade of the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16C750, like the TL16C550C, can be placed in an alternate mode (FIFO mode). This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 64 bytes including three additional bits of error status per byte for the receiver FIFO. The user can choose between a 16-byte FIFO mode or an extended 64-byte FIFO mode. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow through the RTS\ output and the CTS\ input signals (see Figure 1).

特性

• Pin-to-Pin Compatible With the Existing TL16C550B/C
• Programmable 16- or 64-Byte FIFOs to Reduce CPU Interrupts
• Programmable Auto- RTS\ and Auto- CTS\
• In Auto- CTS\ Mode, CTS\ Controls Transmitter
• In Auto- RTS\ Mode, Receiver FIFO Contents and Threshold Control RTS\
• Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power Drop
• Capable of Running With All Existing TL16C450 Software
• After Reset, All Registers Are Identical to the TL16C450 Register Set
• Up to 16-MHz Clock Rate for Up to 1-Mbaud Operation
• In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
• Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (2¹⁶-1) and Generates an Internal 16 × Clock
• Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added or Deleted to or From the Serial Data Stream
• 5-V and 3-V Operation
• Register Selectable Sleep Mode and Low-Power Mode
• Independent Receiver Clock Input
• Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts
• Fully Programmable Serial Interface Characteristics:
  • 5-, 6-, 7-, or 8-Bit Characters
  • Even-, Odd-, or No-Parity Bit Generation and Detection
  • 1-, 11/2-, or 2-Stop Bit Generation