说明
The TL16C2752 is a speed and functional upgrade of the TL16C2552. Since they are pinout and software compatible, designs can easily migrate from the TL16C2552 to the TL16C2752 if needed. The additional functionality within the TL16C2752 is accessed via an extended register set. Some of the key new features are larger receive and transmit FIFOs, embedded IrDA encoders and decoders, RS-485 transceiver controls, software flow control (Xon/Xoff) modes, programmable transmit FIFO thresholds, extended receive and transmit threshold levels for interrupts, and extended receive threshold levels for flow control halt/resume operation.
The TL16C2752 is a dual universal asynchronous receiver and transmitter (UART). It incorporates the functionality of two independent UARTs: each UART having its own register set and transmit and receive FIFOs.
特性
- Larger FIFOs Reduce CPU Overhead
- Programmable Auto-RTS and Auto-CTS
- In Auto-CTS Mode, CTS Controls the Transmitter
- In Auto-RTS Mode, RCV FIFO Contents, and Threshold Control RTS
- Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment is on the Same Power Drop
- Capable of Running With All Existing TL16C450 Software
- After Reset, All Registers Are Identical to the TL16C450 Register Set
- Up to 48-MHz Clock Rate for up to 3-Mbps (Standard 16× Sampling) Operation, or up to
6-Mbps (Optional 8× Sampling) Operation With VCC = 5 V Nominal
- Up to 32-MHz Clock Rate for up to 2-Mbps (Standard 16× Sampling) Operation, or up to
4-Mbps (Optional 8× Sampling) Operation With VCC = 3.3 V Nominal
- Up to 24-MHz Clock Rate for up to 1.5-Mbps (Standard 16× Sampling) Operation, or up to
3-Mbps (Optional 8× Sampling) Operation With VCC = 2.5 V Nominal
- Up to 16-MHz Clock Rate for up to 1-Mbps (Standard 16× Sampling) Operation, or up to 2-Mbps (Optional 8× Sampling) Operation With VCC = 1.8 V Nominal
- In TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
- Programmable Baud-Rate Generator Allows Division of Any Input Reference Clock by 1 to (216 – 1) and Generates an Internal 16× Clock
- Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream
- 5-V, 3.3-V, 2.5-V, and 1.8-V Operation
- Independent Receiver Clock Input
- Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled
- Fully Programmable Serial Interface Characteristics
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit Generation and Detection
