• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The TL16C2552 is a dual universal asynchronous receiver andtransmitter (UART). It incorporates the functionality of two TL16C550D UARTs, each UART having its own register set and FIFOs. The two UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is Asynchronous Communications Element (ACE), and these terms will be used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C2552.

Each ACE is a speed and voltage range upgrade of the TL16C550C, which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode), each ACE can be placed in an alternate FIFO mode.

特性

• Programmable Auto-RTS andAuto-CTS
• In Auto-CTS Mode, CTS Controls the Transmitter
• In Auto-RTS Mode, RCV FIFO Contents, and Threshold Control RTS
• Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment is on the Same Power Drop
• Capable of Running With All Existing TL16C450 Software
• After Reset, All Registers Are Identical to the TL16C450 Register Set
• Up to 24-MHz Clock Rate for up to 1.5-Mbaud Operation With V_CC = 5 V
• Up to 20-MHz Clock Rate for up to 1.25-Mbaud Operation With V_CC = 3.3 V
• Up to 16-MHz Clock Rate for up to 1-Mbaud Operation With V_CC = 2.5 V
• Up to 10-MHz Clock Rate for up to 625-kbaud Operation With V_CC = 1.8 V
• In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
• Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (2¹⁶ - 1) and Generates an Internal 16 × Clock
• Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream
• 5-V, 3.3-V, 2.5-V, and 1.8 V Operation
• Independent Receiver Clock Input
• Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled
• Fully Programmable Serial Interface Characteristics:
  • 5-, 6-, 7-, or 8-Bit Characters
  • Even-, Odd-, or No-Parity Bit Generation and Detection
  • 1-, 1 ½, or 2-Stop Bit Generation