ST10F272M
Features
■ 16-bit CPU with DSP functions
– 50ns instruction cycle time at 40 MHz max
CPU clock
– Multiply/accumulate unit (MAC) 16 x 16-bit
multiplication, 40-bit accumulator
– Enhanced boolean bit manipulations
– Single-cycle context switching support
■ On-chip memories
– 256 Kbyte Flash memory (32-bit fetch)
– Single voltage Flash memories with
erase/program controller and 100 K
erasing/programming cycles.
– Up to 16 Mbyte linear address space for
code and data (5 Mbytes with CAN or I2C)
– 2 Kbyte internal RAM (IRAM)
– 18 Kbyte extension RAM (XRAM)
– Programmable external bus configuration &
characteristics for different address ranges
– 5 programmable chip-select signals
– Hold-acknowledge bus arbitration support
■ Interrupt
– 8-channel peripheral event controller for
single cycle interrupt driven data transfer
– 16-priority-level interrupt system with 56
sources, sampling rate down to 25 ns
■ Timers
– 2 multi-functional general purpose timer
units with 5 timers
■ Two 16-channel capture/compare units
■ Serial channels
– 2 synch./asynch. serial channels
– 2 high-speed synchronous channels
– One I2C standard interface
