SPC560P40L1
Features
■ Up to 64 MHz, single issue, 32-bit CPU core
complex (e200z0h)
– Compliant with Power Architecture®
embedded category
– Variable Length Encoding (VLE)
■ Memory organization
– Up to 256 KB on-chip code flash memory
with ECC and erase/program controller
– Additional 64 (4 × 16) KB on-chip data
flash memory with ECC for EEPROM
emulation
– Up to 20 KB on-chip SRAM with ECC
■ Fail-safe protection
– Programmable watchdog timer
– Non-maskable interrupt
– Fault collection unit
■ Nexus Class 1 interface
■ Interrupts and events
– 16-channel eDMA controller
– 16 priority level controller
– Up to 25 external interrupts
– PIT implements four 32-bit timers
– 120 interrupts are routed via INTC
■ 1 general purpose eTimer unit
– 6 timers each with up/down capabilities
– 16-bit resolution, cascadable counters
– Quadrature decode with rotation direction
flag
– Double buffer input capture and output
compare
■ GPIO (37 on LQFP64; 64 on LQFP100)
individually programmable as I/O or special
function
■ Communications interfaces
– 2 LINFlex channels (1× Master/Slave, 1×
Master only)
