SPC560B54L3
Features
■ High performance 64 MHz e200z0h CPU
– 32-bit Power Architecture® technology CPU
– Up to 60 DMIPs operation
– Variable length encoding (VLE)
■ Memory
– Up to 1.5 MB on-chip Code Flash with ECC
– 64 KB on-chip Data Flash with ECC
– Up to 96 KB on-chip SRAM with ECC
– 8-entry MPU
■ Interrupts
– 16 priority levels
– Non-maskable interrupt (NMI)
– Up to 51 external interrupts lines including
27 wake-up lines
■ 16-channel eDMA (linked to PITs, DSPI,
ADCs, eMIOS, LINFlex and I2C)
■ GPIOs: 77 (LQFP100), 121 (LQFP144) and
149 (LQFP176)
■ Timer units
– 8-channel 32-bit periodic interrupt timer
– 4-channel 32-bit system timer
– System watchdog timer
– Real-time clock timer
■ eMIOS, 16-bit counter timed I/O units
– Up to 64 channels with PWM/MC/IC/OC
– Up to 10 counter basis
– ADC diagnostic trigger via CTU
■ One 10-bit and one 12-bit ADC with up to 53
channels
– Extendable to 81 channels
– Individual conversion registers
– Cross triggering unit (CTU)
■ Dedicated diagnostic module for lighting
– Advanced PWM generation
– Time-triggered diagnostics
– PWM-synchronized ADC measurements
■ On-chip CAN/UART bootstrap loader
■ Communications interfaces
