• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN75LVDS83A FlatLink transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially.

特性

• LVDS Display Serdes Interfaces Directly to LCD Display Panels
  with Integrated LVDS
• Package Options: 8.1mm x 14mm TSSOP
• 3.3V Tolerant Data Inputs
• Transfer Rate up to 100Mpps (Mega Pixel Per Second); Pixel Clock
  Frequency Range 10MHz to 100MHz
• Suited for Display Resolutions Ranging From HVGA up to HD With Low EMI
• Operates From a Single 3.3V Supply and 170mW (typ.) at 75MHz
• 28 Data Channels Plus Clock In Low-Voltage TTL to 4 Data Channels Plus
  Clock Out Low-Voltage Differential
• Consumes Less Than 1mW When Disabled
• Selectable Rising or Falling Clock Edge Triggered Inputs
• ESD: 5kV HBM
• Support Spread Spectrum Clocking (SSC)
• Compatible with all OMAP2x, OMAP™3x, and DaVinci Application Processors
• APPLICATIONS
  • LCD Display Panel Driver
  • UMPC and Netbook PC
  • Digital Picture Frame