• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

This family of four-, eight-, or sixteen-, differential line receivers (with optional integrated termination) implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. Any of the eight or sixteen differential receivers provides a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals almost always requires the use of a line impedance matching resistor at the receiving end of the cable or transmission media.

特性

• Four- ('390), Eight- ('388A), or Sixteen- ('386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
• Integrated 110- Line Termination Resistors on LVDT Products
• Designed for Signaling Rates⁽¹⁾ Up To 200 Mbps
• SN65 Version's Bus-Terminal ESD Exceeds 15 kV
• Operates From a Single 3.3-V Supply
• Typical Propagation Delay Time of 2.6 ns
• Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 ns
• LVTTL Levels Are 5-V Tolerant
• Open-Circuit FailSafe
• Flow-Through Pinout
• Packaged in Thin Shrink Small-Outline
  Package With 20-mil Terminal Pitch

⁽¹⁾ Signaling Rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)