品牌索引 产品分类 > 小信号开关二极管> 瞬态电压抑制器TVS/ESD> 双极管二极管> 调谐二极管> 齐纳(稳压)二极管> 小信号肖特基二极管> 频带转换二极管> 中/高功率管> 射频PIN二极管> Sinterglass二极管> 整流器 > N沟道(N-Channel)> P沟道(P-Channel)> 双N沟道(Dual N-Channel)> 双P沟道(Dual P-Channel)> 双N和P沟道(Dual N and P-Channel)
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产品介绍
特性
DESCRIPTION/ORDERING INFORMATIONThe SN74LV373AT is an octal transparent D-type latch. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |