• Qualified for Automotive Applications
• Typical V_OLP (Output Ground Bounce)
  <0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
  >2.3 V at V_CC = 3.3 V, T_A = 25°C
• Supports Mixed-Mode Voltage Operation on All Ports
• Schmitt-Trigger Circuitry on A, B, and CLR Inputs for Slow Input Transition Rates
• Edge Triggered From Active-High or Active-Low Gated Logic Inputs
• I_off Supports Partial-Power-Down Mode Operation
• Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle
• Overriding Clear Terminates Output Pulse
• Glitch-Free Power-Up Reset on Outputs
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The SN74LV123A is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V V_CC operation.

This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between C_ext and R_ext/C_ext (positive) and an external resistor connected between R_ext/C_ext and V_CC. To obtain variable pulse durations, connect an external variable resistance between R_ext/C_ext and V_CC. The output pulse duration also can be reduced by taking CLR low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-level-active (B) input. Pulse duration can be reduced by taking CLR low. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.

During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free, without applying a reset pulse.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.