特性

  • Will Not Trigger from Clear
  • D-C Triggered from Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses, Up to 100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • 'LS422 Has Internal Timing Resistor

An external timing capacitor may be connected between Cext and Rext/Cext (positive).

To use the internal timing resistor of 'LS422, connect Rint to VCC.

For improved pulse width accuracy and repeatability, connect an external resistor between Rext/Cext and VCC with Rint open-circuited.

To obtain variable pulse widths, connect an external variable resistance between Rint or Rext/Cext and VCC

品牌索引

产品分类

二极管

USB

三极管

可控硅(晶闸管)

场效应管(MOSFET)

集成电路

连接器

LED系列产品

电感器

继电器

传感器

电容器

电阻器

保护器件

光电器件

压电晶体

开关原件

功率模块

FIGURE 1-TYPICAL INPUT/OUTPUT PULSES