These programmable frequency dividers/digital timers contain 31 flip-flops plus 30 gates ('LS292) or 15 flip-flops plus 29 gates ('LS294) on a single chip. The count modulo is under digital control of the inputs provided.

Both types feature an active-low clear input to initialize the state of all flip-flops. To facilitate incoming inspection, test points are provided (TP1, TP2, and TP3 on the 'LS292 and TP on the 'LS294). These test points are not intended to drive system loads. Both types feature two clock inputs; either one may be used for clock gating. (See the function table below.)

A brief look at the digital timing capabilities of the 'LS292 will show that with a 1-MHz input frequency, programming for 2¹⁰ will give a period of 1.024 ms, and 2²⁰ will give a period of 1.05 sec, 2²⁶ will give a period of 1.12 min, and 2³¹ will give a period of 35.79 min.

These devices are easily cascadable giving limitless possibilities to timing delays that can be achieved.