• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The 'ALVTH16821 devices are 20-bit bus-interface flip-flops with 3-state outputs designed for 2.5-V or 3.3-V V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The devices can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

特性

• State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus^TM Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation
• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V V_CC)
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• High-Drive (-24/24 mA at 2.5-V and
  -32/64 mA at 3.3-V V_CC)
• Power Off Disables Outputs, Permitting Live Insertion
• High-Impedance State During Power Up and Power Down Prevents Driver Conflict
• Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
• Auto3-State Eliminates Bus Current Loading When Output Exceeds V_CC + 0.5 V
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method
• Flow-Through Architecture Facilitates Printed Circuit Board Layout
• Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
• Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package

  Widebus is a trademark of Texas Instruments Incorporated.