• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

These 8-bit latches are designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. The Q outputs are designed with bus-driving capability.

The edge-triggered flip-flops enter the data on the low-to-high transition of the clock (CLK) input when the enable () input is low. Data can be read back onto the data inputs by taking the read () input low, in addition to having low. When EN\ is high, both the read-back and write modes are disabled. Transitions on should only be made with CLK high to prevent false clocking.

The polarity of the Q outputs can be controlled by the polarity (T/C\) input. When T/C\ is high, Q is the same as is stored in the flip-flops.

特性

• 3-State I/O-Type Read-Back Inputs
• Bus-Structured Pinout
• T/C\ Determines True or Complementary Data at Q Outputs
• Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs