• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN65MLVD080 and SN65MLVD082 provide eight half-duplex transceivers for transmitting and receiving Multipoint-Low-Voltage Differential Signals in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps. The driver outputs have been designed to support multipoint buses presenting loads as low as 30- and incorporates controlled transition times to allow for stubs off of the backbone transmission line.

The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers (SN65MLVD080) have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2 receivers (SN65MLVD082) implement a failsafe by using an offset threshold.

特性

• Low-Voltage Differential 30- Line Drivers and Receivers for Signaling Rates⁽¹⁾ Up to 250 Mbps; Clock Frequencies Up to 125 MHz
• Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange
• Controlled Driver Output Voltage Transition Times for Improved Signal Quality
• –1 V to 3.4 V Common-Mode Voltage Range Allows Data Transfer With 2 V of Ground Noise
• Bus Pins High Impedance When Driver Disabled or V_CC ≤ 1.5 V
• Independent Enables for each Driver
• Bus Pin ESD Protection Exceeds 8 kV
• Packaged in 64-Pin TSSOP (DGG)
• M-LVDS Bus Power Up/Down Glitch Free
• APPLICATIONS
  • Parallel Multipoint Data and Clock Transmission Via Backplanes and Cables
  • Low-Power High-Speed Short-Reach Alternative to TIA/EIA-485
  • Cellular Base Stations
  • Central-Office Switches
  • Network Switches and Routers

⁽¹⁾The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).