• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended LVTTL synchronous data at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data.

特性

• 4:28 Data Channel Expansion at up to 1.904 Gigabits per Second Throughput
• Suited for Point-to-Point Subsystem Communication With Very Low EMI
• 4 Data Channels and Clock Low-Voltage Differential Channels in and 28 Data and Clock Out Low-Voltage TTL Channels Out
• Operates From a Single 3.3-V Supply and 250 mW (Typ)
• 5-V Tolerant SHTDN\ Input
• Rising Clock Edge Triggered Outputs
• Bus Pins Tolerate 4-kV HBM ESD
• Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch
• Consumes <1 mW When Disabled
• Wide Phase-Lock Input Frequency Range
  20 MHz to 65 MHz
• No External Components Required for PLL
• Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard
• Industrial Temperature Qualified T_A = -40°C to 85°C
• Replacement for the DS90CR286