• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN65LVDS93 LVDS serdes (serializer/ deserializer) transmitter contains four 7-bit parallel- load serial-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices.

特性

• 28:4 Data Channel Compression at up to 1.904 Gigabits per Second Throughput
• Suited for Point-to-Point Subsystem Communication With Very Low EMI
• 28 Data Channels Plus Clock in Low-Voltage TTL and 4 Data Channels Plus Clock Out Low-Voltage Differential
• Selectable Rising or Falling Clock Edge Triggered Inputs
• Bus Pins Tolerate 6-kV HBM ESD
• Operates From a Single 3.3-V Supply and 250 mW (Typ)
• 5-V Tolerant Data Inputs
• Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch
• Consumes <1 mW When Disabled
• Wide Phase-Lock Input Frequency Range 20 MHz to 68 MHz
• No External Components Required for PLL
• Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
• Industrial Temperature Qualified T_A = -40°C to 85°C
• Replacement for the DS90CR285