• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN65LVDS311 serializer transmits 27 parallel input data over 1, 2, or 3 serial output links. The device pinout is optimized to interface with the OMAP3630 application processor. The device loads a shift register with the 24 pixel bits and 3 control bits from the parallel CMOS input interface. The data are latched into the device by the pixel clock, PCLK. In addition to the 27 bits, the device adds a parity bit and two reserved bits for a total number of 30 serial bits. The parity bit allows a receiver to detect single-bit errors. Odd parity is implemented.

The serial shift register is uploaded through 1, 2, or 3 serial outputs at 30, 15, or 10 times the pixel clock data rate. A copy of the pixel clock is output on an additional differential output.

特性

• 2.8 × 2.8mm package size
• 1.8V input signal swing
• 24-Bit RGB Data, 3 Control Bits, 1 Parity Bit and 2 Reserved Bits
  Transmitted over 1, 2 or 3 Differential Lines
• SubLVDS Differential Voltage Levels
• Three Operating Modes to Conserve Power
  • Active-Mode QVGA 17.4mW (typ)
  • Active-Mode VGA 28.8mW (typ)
  • Shutdown Mode 0.5µ (typ)
  • Standby Mode 0.5µA (typ)
• ESD Rating > 3kV (HBM)
• Pixel Clock Range of 4MHz–65MHz
• Failsafe on all CMOS Inputs
• Typical Application: Smartphone