• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN65LVDS307 serializer device converts 27 parallel data inputs to one or two sub-low-voltage differential signaling (SubLVDS) serial outputs. It loads a shift register with 24 pixel bits and 3 control bits from the parallel CMOS input interface. In addition to the 27 data bits, the device adds a parity bit and two reserved bits into a 30-bit data word. Each word is latched into the device by the pixel clock (PCLK). The parity bit (odd parity) allows a receiver to detect single bit errors. The serial shift register is uploaded at 30 or 15 times the pixel-clock data rate, depending on the number of serial links used. A copy of the pixel clock is output on a separate differential output.

FPC cabling typically interconnects the SN65LVDS307 with the display.

特性

• FlatLink 3G Serial-Interface Technology
• Compatible With FlatLink™ 3G Receivers Such as SN65LVDS308
• Input Supports Video Interfaces up to 24-Bit RGB Data and 3 Control Bits Received Over Two Differential Data Lines
• SubLVDS Differential Voltage Levels
• Up to 810-Mbps Data Throughput
• Three Operating Modes to Conserve Power
  • Active-Mode QVGA, 60 fps, 17.4 mW (typ)
  • Active-Mode VGA, 60 fps, 28.8 mW (typ)
  • Shutdown Mode 0.9 µW (typ)
• 1.8-V Supply Voltage
• ESD Rating > 3 kV (HBM)
• Pixel Clock Range of 4 MHz-30 MHz
• Failsafe on All CMOS Inputs
• 4-mm × 4-mm MicroStar Junior™ µBGA® Package With 0,5-mm Ball Pitch
• Very Low EMI
• APPLICATIONS
  • Host-Controller to Display-Module Interface
  • Mobile Phones and Smart Phones
  • Portable Multimedia Players

FlatLink, MicroStar Junior are trademarks of Texas Instruments.
µBGA is a registered trademark of Tessera, Inc..
All other trademarks are the property of their respective owners.