• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN65LVDS306 receiver deserializes FlatLink™3G-compliant serial input data to 27 parallel data outputs. The SN65LVDS306 receiver contains one shift register to load 30 bits from one serial input and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If the parity check confirms correct parity, the channel parity error (CPE) output remains low. If a parity error is detected, the CPE output generates a high pulse while the data output bus disregards the newly-received pixel. Instead, the last data word is held on the output bus for another clock cycle.

The serial data and clock are received via sub-low-voltage differential signalling (SubLVDS) lines. The SN65LVDS306 supports three operating power modes (shutdown, standby, and active) to conserve power.

特性

• Serial Interface Technology
• Compatible With FlatLink™3G Such as SN65LVDS305
• Supports Video Interfaces up to 24-Bit RGB Data and 3 Control Bits Received Over One SubLVDS Differential Line
• SubLVDS Differential Voltage Levels
• Up to 405-Mbps Data Throughput
• Three Operating Modes to Conserve Power
  • Active mode QVGA: 17 mW
  • Typical Shutdown: 0.7 µW
  • TypicalStandby Mode: 27 µW Typical
• Bus-Swap Function for PCB-Layout Flexibility
• ESD Rating > 4 kV (HBM)
• Pixel Clock Range of 4 MHz-15 MHz
• Failsafe on all CMOS Inputs
• Packaged in 5-mm × 5-mm MicroStar Junior µBGA® With 0,5-mm Ball Pitch
• Very Low EMI Meets SAE J1752/3 Kh-Spec
• APPLICATIONS
  • Small Low-Emission Interface Between Graphics Controller and LCD Display
  • Mobile Phones and Smart Phones
  • Portable Multimedia Players

FlatLink is a trademark of Texas Instruments.
µBGA is a registered trademark of Tessera, Inc.