• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN65LVDS305 serializer device converts 27 parallel data inputs to one sub-low-voltage differential signaling (SubLVDS) serial output. It loads a shift register with 24 pixel bits and 3 control bits from the parallel CMOS input interface. In addition to the 27 data bits, the device adds a parity bit and two reserved bits into a 30-bit data word. Each word is latched into the device by the pixel clock (PCLK). The parity bit (odd parity) allows a receiver to detect single bit errors. The serial shift register is uploaded at 30 times the pixel-clock data rate. A copy of the pixel clock is output on a separate differential output.

FPC cabling typically interconnects the SN65LVDS305 with the display. Compared to parallel signaling, the SN65LVDS305 outputs reduce the EMI of the interconnect by over 20 dB.

特性

• FlatLink™3G Serial-Interface Technology
• Compatible With FlatLink3G Receivers Such as SN65LVDS306
• Input Supports 24-bit RGB Video Mode Interface
• 24-Bit RGB Data, 3 Control Bits, 1 Parity Bit, and 2 Reserved Bits Transmitted Over One Differential Line
• SubLVDS Differential Voltage Levels
• Effective Data Throughput up to 405 Mbps
• Three Operating Modes to Conserve Power
  • Active-Mode QVGA 17.4 mW (Typical)
  • Shutdown Mode 0.5 µA (Typical)
• Bus Swap for Increased PCB Layout Flexibility
• 1.8-V Supply Voltage
• ESD Rating > 2 kV (HBM)
• Typical Application: Host-Controller to Display-Module Interface
• Pixel Clock Range of 4 MHz-15 MHz
• Failsafe on all CMOS Inputs
• Packaging: 80-Terminal 5-mm × 5-mm µBGA®

FlatLink is a trademark of Texas Instruments.
µBGA is a registered trademark of Tessera, Inc.