• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN65LVDS22 and SN65LVDM22 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The receiver outputs can be switched to either or both drivers through the multiplexer control signals S0 and S1. This allows the flexibility to perform splitter or signal routing functions with a single device.

The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100- load.

The intended application of these devices and signaling technique is for both point-to-point baseband (single termination) and multipoint (double termination) data transmissions over controlled impedance media.

特性

• Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard
• Designed for Clock Rates up to 200 MHz (400 Mbps)
• Designed for Data Rates up to 250 Mbps
• Pin Compatible With SN65LVDS122 and SN65LVDT122, 1.5 Gbps 2x2 Crosspoint Switch From TI
• ESD Protection Exceeds 12 kV on Bus Pins
• Operates From a Single 3.3-V Supply
• Low-Voltage Differential Signaling With Output Voltages of 350 mV Into:
  • 100- Load (SN65LVDS22)
  • 50- Load (SN65LVDM22)
• Propagation Delay Time; 4 ns Typ
• Power Dissipation at 400 Mbps of 150 mW
• Bus Pins Are High Impedance When Disabled or With V_CC Less Than 1.5 V
• LVTTL Levels Are 5 V Tolerant
• Open-Circuit Fail Safe Receiver