• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.

The outputs of the SN65LVDS100 and SN65LVDT100 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDS101 and SN65LVDT101 are compatible with 3.3-V PECL levels. Both drive differential transmission lines with nominally 100- characteristic impedance.

特性

• Designed for Signaling Rates⁽¹⁾ ≥ 2 Gbps
• Total Jitter < 65 ps
• Low-Power Alternative for the MC100EP16
• Low 100 ps (Max) Part-To-Part Skew
• 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range
• Inputs Electrically Compatible With LVPECL, CML, and LVDS Signal Levels
• 3.3-V Supply Operation
• LVDT Integrates 110- Terminating Resistor
• Offered in SOIC and MSOP
• APPLICATIONS
  • 622 MHz Central Office Clock Distribution
  • High-Speed Network Routing
  • Wireless Basestations
  • Low Jitter Clock Repeater
  • Serdes LVPECL Output to FPGA LVDS Input Translator

⁽¹⁾The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).