• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN65LVDM320 is an 8-bit data storage register with differential line drivers and receivers that are electrically compatible with ANSI EIA/TIA-644 for multipoint architectures with standard-compliant parallel transfer rates of 475 Mbps. The SN65LVDM320 includes transmitter and receiver data registers that remain active regardless of the state of their associated outputs.

The logic element for data flow in each direction is configured by mode-control inputs. IMODE1 and IMODE2 control data flow in the B-to-A (bus side to digital side) direction when configured as a buffer, a D-type flip-flop, or a D-type latch. OMODE1 and OMODE2 control data flow in each of the operating modes for the A-to-B (digital side to bus side) direction.

特性

• 8-Bit Bidirectional Data Storage Register With Full Parallel Access
• Parallel Transfer Rates
  • Buffer Mode: Up to 475 Megatransfers
  • Flip-Flop Mode: Up to 300 Megatransfers
  • Latch Mode: Up to 300 Megatransfers
• Operates With a Single 3.3-V Supply
• Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV Across a 50- Load
• Bus and Logic Loopback Capability
• Very Low Radiation Emission
• Low Skew Performance
  • Pulse Skew Less Than 100 ps
  • Output Skew Less Than 320 ps
  • Part-to-Part Skew Less Than 1 ns
• Open-Circuit Differential Receiver Fail Safe Assures a Low-Level Output
• Reset at Power Up
• 12-kV Bus-Pin ESD Protection
• Bus Pins Remain High-Impedance When Disabled or With V_CC Below 1.5 V for Power-Up/Down Glitch-Free Performance and Hot Plugging
• 5-V Tolerant LVCMOS Inputs
• APPLICATIONS
  • Telecom Switching