• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN65LVDM179, SN65LVDM180, SN65LVDM050, and SN65LVDM051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve high signaling rates. These circuits are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts, except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV across a 50- load simulating two transmission lines in parallel. This allows having data buses with more than one driver or with two line termination resistors. The receivers detect a voltage difference of 50 mV with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of these devices and signaling techniques is point-to-point half duplex, baseband data transmission over a controlled impedance media of approximately 100 characteristic impedance.

特性

• Low-Voltage Differential 50- Line Drivers and Receivers
• Typical Full-Duplex Signaling Rates of 100 Mbps
• Bus-Terminal ESD Exceeds 12 kV
• Operates From a Single 3.3-V Supply
• Low-Voltage Differential Signaling With Typical
  Output Voltages of 340 mV With a 50- Load
• Valid Output With as Little as 50-mV Input
  Voltage Difference
• Propagation Delay Times
  • Driver: 1.7 ns Typical
  • Receiver: 3.7 ns Typical
• Power Dissipation at 200 MHz
  • Driver: 50 mW Typical
  • Receiver: 60 mW Typical
• LVTTL Input Levels Are 5-V Tolerant
• Driver Is High Impedance When Disabled or With V_CC < 1.5 V
• Receiver Has Open-Circuit Failsafe