• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput.

Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.

The device can be entered into a power-down state when no data transfer is required.

特性

• 100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz
  to 66-MHz System Clock
• Pin-Compatible Superset of DS92LV1023/DS92LV1224
• Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz
• Synchronization Mode for Faster Lock
• Lock Indicator
• No External Components Required for PLL
• 28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available
• Industrial Temperature Qualified,
  T_A = −40°C to 85°C
• Programmable Edge Trigger on Clock
• Flow-Through Pinout for Easy PCB Layout
• APPLICATIONS
  • Wireless Base Station
  • Backplane Interconnect
  • DSLAM