• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN65ELT21 is a differential PECL-to-TTL translator. It operates on +5-V supply and ground only. The device includes circuitry to maintain Q to a low logic level when inputs are in an open condition or < 1.3 V.

The V_BB pin is a reference voltage output for the device. When the device is used in single-ended mode, the unused input should be tied to V_BB. This reference voltage can also be used to bias the input when it is ac coupled. When it is used, place a 0.01µF decoupling capacitor between V_CC and V_BB. Also limit the sink/source current to < 0.5 mA to V_BB. Leave V_BB open when it is not used.

The SN65ELT21 is housed in an industry standard SOIC-8 package and is also available in an optional TSSOP-8 package.

特性

• 3ns (TYP) Propagation Delay
• Operating Range: V_CC = 4.2 V to 5.7 V with GND = 0 V
• 24-mA TTL Output
• Deterministic Output Value for Open Input Conditions or When Inputs < 1.3 V
• Built-In Temperature Compensation
• Drop-In Compatible to the MC10ELT21, MC100ELT21
• APPLICATIONS
  • Data and Clock Transmission Over Backplane
  • Signaling Level Conversion for Clock or Data