• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

The SN65EL16 is a differential PECL/ECL receiver with PECL/ECL output. The device includes circuitry to hold Q to a low logic level when the inputs are in an open condition.

The V_BB pin is a reference voltage output for the device. When the device is used in the single-ended mode, the unused input should be tied to V_BB. This reference voltage can also be used to bias the input when it is ac coupled. When the V_BB pin is used, place a 0.01-µF decoupling capacitor between V_CC and V_BB. Also, limit the sink/source current to <0.5 mA to V_BB. Leave V_BB open when it is not used.

The SN65EL11 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 package.

特性

• Differential PECL/NECL Receiver
• Operating Range
  • PECL: V_CC = 4.2 V to 5.7 V With V_EE = 0 V
  • NECL: V_CC = 0 V With V_EE = -4.2 V to -5.7 V
• 250-ps Propagation Delay
• Support for Clock Frequencies >2 GHz
• Deterministic Output Value for Open Input Conditions
• Built-In Temperature Compensation
• Drop-In Compatible With MC10EL16, MC100EL16
• Built-In Input Pulldown Resistors
• APPLICATIONS
  • Data and Clock Transmission Over Backplane