• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:

• Inhibit clock (do nothing)
• Shift right (in the direction Q_A toward Q_D)
• Shift left (in the direction Q_D toward Q_A)
• Parallel (broadside) load

Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input.

特性

• Parallel Inputs and Outputs
• Four Operating Modes:
  • Synchronous Parallel Load
  • Right Shift
  • Left Shift
  • Do Nothing
• Positive Edge-Triggered Clocking
• Direct Overriding Clear