• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

These 8-bit universal shift/storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1\, OE2\) inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs asynchronously when the clear (CLR\) input is low. Taking either OE1\ or OE2\ high disables the outputs, but has no effect on clearing, shifting, or storing data.

特性

• Multiplexed I/O Ports Provide Improved Bit Density
• Four Modes of Operation:
  • Hold (Store)
  • Shift Right
  • Shift Left
  • Load Data
• Operate With Outputs Enabled or at High Impedance
• 3-State Outputs Drive Bus Lines Directly
• Can Be Cascaded for n-Bit Word Lengths
• Direct Overriding Clear
• Applications:
  • Stacked or Push-Down Registers
  • Buffer Storage
  • Accumulator Registers
• Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs