• - 交流-直流(AC-DC)控制器和稳压器
• - 直流-直流(DC-DC)控制器、转换器和稳压器
• - 电压和电流管理
• - 通讯IC
• - 驱动器
• - 热管理

• - 时钟及数据分配
• - 标准逻辑

• - 放大器和比较器
• - 模拟开关
• - 数字电位计
• - 接口
• - EMI和RFI滤波器

• - EEPROM存储器
• - 非易失性只读存储器(NVRAM)
• - SRAM存储器

说明

These J-K flip-flops are based on the master-slave principle and each has AND gate inputs for entry into the master section which are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows:

• 1. Isolate slave from master
• 2. Enter information from AND gate inputs to master
• 3. Disable AND gate inputs
• 4. Transfer information from master to slave

The logical states of the J and K inputs must not be allowed to change when the clock pulse is in a high state.

The SN5472, and the SN54H72 are characterized for operation over the full military temperature range of -55°C to 125°C.

特性

• Packages Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages
• Dependable Texas Instruments Quality and Reliability