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首 页 > 新闻动态 > 公司新闻 > 供应 PCI4510GHK TI BGA 层控制器 供应 PCI4510GHK TI BGA 层控制器Card Standard 8.0 compliant i.LINK™ implementations of IEEE Std 1394
· PCI Bus Power Management Interface · Compliant with Intel Mobile Power Guideline Specification 1.1 compliant 2000 · Advanced Configuration and Power Interface · Full IEEE Std 1394a-2000 support includes: Specification 2.0 compliant connection debounce, arbitrated short reset, · PCI Local Bus Specification Revision 2.2 multispeed concatenation, arbitration compliant acceleration, fly-by concatenation, and port disable/suspend/resume · PC 98/99 and PC2001 compliant · Power-down features to conserve energy in · Compliant with the PCI Bus Interface battery-powered applications include: Specification for PCI-to-CardBus Bridges automatic device power down during · Fully compliant with provisions of IEEE Std suspend, PCI power management for 1394-1995 for a high-performance serial bus link-layer and inactive ports powered down, and IEEE Std 1394a-2000 ultralow-power sleep mode · Fully compliant with 1394 Open Host · Two IEEE Std 1394a-2000 fully compliant Controller Interface Specification 1.1 cable ports at 100M bits/s, 200M bits/s, and · Compatible with both TPS2211A and 400M bits/s TPS2221 PC Card power switches · Cable ports monitor line conditions for active · 1.8-V core logic and 3.3-V I/O cells with connection to remote node internal voltage regulator to generate 1.8-V · Cable power presence monitoring core VCC · Separate cable bias (TPBIAS) for each port · Universal PCI interfaces compatible with · Physical write posting of up to three 3.3-V and 5-V PCI signaling environments outstanding transactions · Supports PC Card or CardBus with hot · PCI burst transfers and deep FIFOs to insertion and removal tolerate large host latency · Supports 132-MBps burst transfers to · External cycle timer control for customized maximize data throughput on both the PCI synchronization bus and the CardBus · Extended resume signaling for compatibility · Supports serialized IRQ with PCI interrupts with legacy DV components · Programmable multifunction terminals · PHY-Link logic performs system initialization · Serial ROM interface for loading subsystem and arbitration functions ID and subsystem vendor ID · PHY-Link encode and decode functions · ExCA-compatible registers are mapped in included for data-strobe bit level encoding memory or I/O space · PHY-Link incoming data resynchronized to · Intel 82365SL–DF register compatible local clock · Supports ring indicate, SUSPEND, PCI · Low-cost 24.576-MHz crystal provides CCLKRUN protocol, and PCI bus lock (LOCK) transmit and receive data at 100M bits/s, · Provides VGA/palette memory and I/O, and 200M bits/s, and 400M bits/s subtractive decoding options, LED activity · Node power class information signaling for terminals |
