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首 页 > 新闻动态 > 公司新闻 > 供应 NXP 74HC573 八进制D型透明锁存 供应 NXP 74HC573 八进制D型透明锁存74HC573 Octal D-type transparent latch; 3-stateThe 74HC573; 74HCT573 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC573; 74HCT573 has octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are transparent, i.e. a latch output changes state each time its corresponding D input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74HC573; 74HCT573 is functionally identical to: • 74HC563; 74HCT563, but inverted outputs • 74HC373; 74HCT373, but different pin arrangement  |
