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首 页 > 新闻动态 > 公司新闻 > 供应 TL16C554A 具有16字节FIFO接口
供应 TL16C554A 具有16字节FIFO接口
特性
- Integrated Asynchronous Communications Element
- Consists of Four Improved TL16C550 ACEs Plus Steering Logic
- In FIFO Mode, Each ACE Transmitter and Receiver Is Buffered With 16-Byte FIFO to Reduce the Number of Interrupts to CPU
- In TL16C450 Mode, Hold and Shift Registers Eliminate Need for Precise Synchronization Between the CPU and Serial Data
- Up to 16-MHz Clock Rate for up to 1-Mbaud Operation
- Programmable Baud Rate Generators Which Allow Division of Any Input Reference Clock by 1 to (216-1) and Generate an Internal 16 × Clock
- Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or From the Serial Data Stream
- Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts
- Fully Programmable Serial Interface Characteristics:
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit
- 1-, 1 1/2-, or 2-Stop Bit Generation
- Baud Generation (DC to 1-Mbit Per Second)
- False Start Bit Detection
- Complete Status Reporting Capabilities
- Line Break Generation and Detection
- Internal Diagnostic Capabilities:
- Loopback Controls for Communications Link Fault Isolation
- Break, Parity, Overrun, Framing Error Simulation
- Fully Prioritized Interrupt System Controls
- Modem Control Functions (CTS\, RTS\, DSR\, DTR\, RI\, and DCD\)
- 3-State Outputs Provide TTL Drive Capabilities for Bidirectional Data Bus and Control Bus
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