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首 页 > 新闻动态 > 公司新闻 > 供应 PCI4510GH 链路层控制器
供应 PCI4510GH 链路层控制器
PCI4510GH
特性
- PC Card Standard 8.0 compliant
- PCI Bus Power Management Interface Specification 1.1 compliant
- Advanced Configuration and Power Interface Specification 2.0 compliant
- PCI Local Bus Specification Revision 2.2 compliant
- PC 98/99 and PC2001 compliant
- Compliant with the PCI Bus Interface Specification for PCI-to-CardBus Bridges
- Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std 1394a-2000
- Fully compliant with 1394 Open Host Controller Interface Specification 1.1
- Compatible with both TPS2211A and TPS2221 PC Card power switches
- 1.8-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.8-V core VCC
- Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
- Supports PC Card or CardBus with hot insertion and removal
- Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus
- Supports serialized IRQ with PCI interrupts
- Programmable multifunction terminals
- Serial ROM interface for loading subsystem ID and subsystem vendor ID
- ExCA-compatible registers are mapped in memory or I/O space
- Intel 82365SL–DF register compatible
- Supports ring indicate, SUSPEND\, PCI CCLKRUN\ protocol, and PCI bus lock (LOCK)\
- Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity terminals
- Fully interoperable with FireWire™ and i.LINK™ implementations of IEEE Std 1394
- Compliant with Intel Mobile Power Guideline 2000
- Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume
- Power-down features to conserve energy in battery-powered applications include: automatic device power down during suspend, PCI power management for link-layer and inactive ports powered down, ultralow-power sleep mode
- Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s
- Cable ports monitor line conditions for active connection to remote node
- Cable power presence monitoring
- Separate cable bias (TPBIAS) for each port
- Physical write posting of up to three outstanding transactions
- PCI burst transfers and deep FIFOs to tolerate large host latency
- External cycle timer control for customized synchronization
- Extended resume signaling for compatibility with legacy DV components
- PHY-Link logic performs system initialization and arbitration functions
- PHY-Link encode and decode functions included for data-strobe bit level encoding
- PHY-Link incoming data resynchronized to local clock
- Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and 400M bits/s
- Node power class information signaling for system power management
- Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std 1394a-2000 features
- Isochronous receive dual-buffer mode
- Out-of-order pipelining for asynchronous transmit requests
- Register access fail interrupt when the PHY SCLK is not active
- PCI power-management D0, D1, D2, and D3 power states
- Initial bandwidth available and initial channels available registers
- PME\ support per 1394 Open Host Controller Interface Specification
- Advanced submicron, low-power CMOS technology
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