品牌索引
产品分类 > 小信号开关二极管> 瞬态电压抑制器TVS/ESD> 双极管二极管> 调谐二极管> 齐纳(稳压)二极管> 小信号肖特基二极管> 频带转换二极管> 中/高功率管> 射频PIN二极管> Sinterglass二极管> 整流器 > N沟道(N-Channel)> P沟道(P-Channel)> 双N沟道(Dual N-Channel)> 双P沟道(Dual P-Channel)> 双N和P沟道(Dual N and P-Channel)
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产品介绍 Features
• Maximum Input Clock Frequency > 3.5 GHz Typical • Differential CLK Clock Input • Differential CE Clock Enable Input • Differential SEL Word Select Input • 50 Internal Input and Output Termination Resistors • Differential TC Terminal Count Output • All Outputs 16 mA CML with 50 Internal Source Termination to VCC • All Single–Ended Control Pins CMOS and PECL/NECL Compatible • Counter Programmed Using One of Two Single−Ended Words, Pa[0:7] and Pb[0:7], Stored in REGa and REGb • REGa and REGb Implemented with Level Triggered Latch • Compatible with Existing 3.3 V LVEP, EP, and SG Devices • Ability to Program the Divider without Disturbing Current Settings • Positive CML Output Operating Range: VCC = 3.0 V to 3.465 V with VEE = 0 V • Negative CML Output Operating Range: VCC = 0 V with VEE = –3.0 V to –3.465 V • VBB Reference Voltage Output • CML Output Level: 400 mV Peak−Peak Output with 50 Receiver Resistor to VCC • Pb−Free Packages are Available* |
